Electrically erasable and programmable memory devices having arrays of what are known as flash cells are found in a wide variety of electrical devices. A flash cell, also called a floating gate transistor memory cell, is similar to a field effect transistor, having a channel region between a source and a drain and a control gate over the channel region. In addition the flash cell has a floating gate between the control gate and the channel region. The floating gate is typically separated from the channel region by a layer of gate oxide, and an inter-poly dielectric layer typically separates the control gate from the floating gate. Both the control gate and the floating gate are typically formed of doped polysilicon. The floating gate remains floating or electrically isolated. A flash cell is programmed by applying appropriate voltages to the control gate, the drain, and the source to cause electrons to pass from the channel region to the floating gate through the gate oxide. The voltage at the control gate determines the amount of charge residing on the floating gate after programming, and the charge determines the voltage that must be applied to the control gate in order to allow the flash cell to conduct current between the source and the drain. This voltage is termed the threshold voltage of the flash cell, and is the physical form of the data stored in the flash cell. As the charge on the floating gate increases the threshold voltage increases.
An alternative to the above described semiconductor memory device is an electrically erasable and programmable memory device having arrays of multi-bit or multi-state flash cells. Multi-state flash cells have the same structure as ordinary flash cells and are capable of storing multiple bits of data in a single cell. A multi-bit or multi-state flash cell has multiple distinct threshold voltage levels over a voltage range. Each distinct threshold voltage level corresponds to a set of data bits, with the number of bits representing the amount of data which can be stored in the multi state flash cell.
Data is conventionally stored in semiconductor memory devices based on flash cells by programming flash cells that have been previously erased. A flash cell is erased by applying appropriate voltages to the control gate and the source of the flash cell and allowing the drain to float. The electrons in the floating gate are induced to pass through the gate oxide to the source such that the charge in the floating gate is reduced and the threshold voltage of the flash cell is reduced.
Flash cells in an array are conventionally erased in blocks in an erase procedure. Ideally, each erased flash cell in a block has a threshold voltage within a specified voltage range. Unfortunately in each block some flash cells may become overerased after an erase procedure. An overerased flash cell has insufficient negative charge in the floating gate, and in some cases may have a net positive charge in the floating gate, and therefore has a threshold voltage that is too low. The overerased flash cell will be activated with a very low positive voltage applied to the control gate, even as low as a ground voltage, and may leak current even though it is not being read or verified. Leaking current is current that is allowed to pass through the flash cell when the flash cell is not intended to be conductive. The current from leaking flash cells makes it impossible to read other flash cells accurately if they share a bit line, the line connecting the drains of adjacent flash cells to the sense amplifier. The flash cells connected to the same bit line are considered to be in the same column of an array. A leaky column has leaking flash cells connected to the bit line in the column.
Flash cells are read by grounding the source, applying a low positive voltage to the drain and a higher positive voltage to the control gate. If the control gate voltage exceeds its threshold voltage the flash cell will be activated to conduct current. A flash cell that conducts current while being read is in an erased state. If the flash cell is programmed its threshold voltage is high and it will not conduct current while being read. A sense amplifier is used to sense the presence of current through the flash cell. Flash cells are verified as being erased in a verification operation in which the flash cells are read individually in a sequence.
A conventional method 50 of erasing flash cells in an array is shown in FIG. 1. In step 52 an erase pulse is applied to a block of flash cells in the array. A verification operation is performed for the block in step 54 to determine if each of the flash cells in the block has a threshold voltage below a specified threshold voltage. If the erasure of all of the flash cells in the block cannot be determined in step 56, erase pulses are reapplied in step 52 until each of the flash cells in the block has a threshold voltage below the specified threshold voltage.
Some flash cells become overerased due to the repeated application of erase pulses. A heal operation is performed in step 58 to correct overerased flash cells. In the heal operation the drains of the flash cells in a block are left floating, the sources are grounded, and a high voltage pulse, called a heal pulse, is applied to the control gates to draw electrons to the floating gates. Flash cells that have been overerased will draw more negative charge to their respective control gates than the flash cells that were not overerased so that all of the flash cells in the block will have their respective threshold voltage levels raised to a similar level. Several heal pulses may be applied to the block of flash cells to reduce the distribution of threshold voltage levels. Following the application of one or more heal pulses in step 58 the method 50 ends with step 60.
The conventional method 50 of erasing flash cells in an array can result in overheated flash cells in the block. Accordingly, there exists a need for a method of erasing flash cells that minimizes the creation of overhealed flash cells. For these and other reasons, there is a need for the present invention.